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https://github.com/facebook/rocksdb.git
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d9cd33516a
Summary: UBSAN shows following warning: util/crc32c_arm64.cc:111:11: runtime error: load of misaligned address 0x00001afcda86 for type 'const uint64_t', which requires 8 byte alignment 0x00001afcda86: note: pointer points here cc c1 2d 00 01 81 40 24 30 66 39 66 30 37 30 63 2d 32 36 63 34 2d 34 62 61 61 2d 38 35 33 31 2d ^ Suppress it just as what we do in x86 CRC. Pull Request resolved: https://github.com/facebook/rocksdb/pull/6827 Test Plan: Run the same UBSAN and see it to pass now. Reviewed By: ltamasi Differential Revision: D21471838 fbshipit-source-id: 02943dd39a7030d2b03e5d894dcb23ed72b6c9c3
143 lines
3.7 KiB
C++
143 lines
3.7 KiB
C++
// Copyright (c) 2018, Arm Limited and affiliates. All rights reserved.
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// This source code is licensed under both the GPLv2 (found in the
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// COPYING file in the root directory) and Apache 2.0 License
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// (found in the LICENSE.Apache file in the root directory).
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#include "util/crc32c_arm64.h"
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#if defined(__linux__) && defined(HAVE_ARM64_CRC)
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#include <asm/hwcap.h>
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#ifdef ROCKSDB_AUXV_GETAUXVAL_PRESENT
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#include <sys/auxv.h>
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#endif
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#ifndef HWCAP_CRC32
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#define HWCAP_CRC32 (1 << 7)
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#endif
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#ifdef HAVE_ARM64_CRYPTO
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/* unfolding to compute 8 * 3 = 24 bytes parallelly */
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#define CRC32C24BYTES(ITR) \
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crc1 = crc32c_u64(crc1, *(buf64 + BLK_LENGTH + (ITR))); \
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crc2 = crc32c_u64(crc2, *(buf64 + BLK_LENGTH * 2 + (ITR))); \
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crc0 = crc32c_u64(crc0, *(buf64 + (ITR)));
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/* unfolding to compute 24 * 7 = 168 bytes parallelly */
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#define CRC32C7X24BYTES(ITR) \
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do { \
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CRC32C24BYTES((ITR)*7 + 0) \
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CRC32C24BYTES((ITR)*7 + 1) \
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CRC32C24BYTES((ITR)*7 + 2) \
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CRC32C24BYTES((ITR)*7 + 3) \
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CRC32C24BYTES((ITR)*7 + 4) \
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CRC32C24BYTES((ITR)*7 + 5) \
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CRC32C24BYTES((ITR)*7 + 6) \
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} while (0)
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#endif
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uint32_t crc32c_runtime_check(void) {
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#ifdef ROCKSDB_AUXV_GETAUXVAL_PRESENT
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uint64_t auxv = getauxval(AT_HWCAP);
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return (auxv & HWCAP_CRC32) != 0;
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#else
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return 0;
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#endif
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}
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#ifdef ROCKSDB_UBSAN_RUN
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#if defined(__clang__)
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__attribute__((__no_sanitize__("alignment")))
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#elif defined(__GNUC__)
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__attribute__((__no_sanitize_undefined__))
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#endif
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#endif
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uint32_t crc32c_arm64(uint32_t crc, unsigned char const *data,
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unsigned len) {
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const uint8_t *buf8;
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const uint64_t *buf64 = (uint64_t *)data;
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int length = (int)len;
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crc ^= 0xffffffff;
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#ifdef HAVE_ARM64_CRYPTO
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/* Crc32c Parallel computation
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* Algorithm comes from Intel whitepaper:
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* crc-iscsi-polynomial-crc32-instruction-paper
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*
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* Input data is divided into three equal-sized blocks
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* Three parallel blocks (crc0, crc1, crc2) for 1024 Bytes
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* One Block: 42(BLK_LENGTH) * 8(step length: crc32c_u64) bytes
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*/
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#define BLK_LENGTH 42
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while (length >= 1024) {
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uint64_t t0, t1;
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uint32_t crc0 = 0, crc1 = 0, crc2 = 0;
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/* Parallel Param:
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* k0 = CRC32(x ^ (42 * 8 * 8 * 2 - 1));
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* k1 = CRC32(x ^ (42 * 8 * 8 - 1));
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*/
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uint32_t k0 = 0xe417f38a, k1 = 0x8f158014;
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/* Prefetch data for following block to avoid cache miss */
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PREF1KL1((uint8_t *)buf64, 1024);
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/* First 8 byte for better pipelining */
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crc0 = crc32c_u64(crc, *buf64++);
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/* 3 blocks crc32c parallel computation
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* Macro unfolding to compute parallelly
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* 168 * 6 = 1008 (bytes)
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*/
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CRC32C7X24BYTES(0);
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CRC32C7X24BYTES(1);
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CRC32C7X24BYTES(2);
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CRC32C7X24BYTES(3);
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CRC32C7X24BYTES(4);
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CRC32C7X24BYTES(5);
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buf64 += (BLK_LENGTH * 3);
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/* Last 8 bytes */
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crc = crc32c_u64(crc2, *buf64++);
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t0 = (uint64_t)vmull_p64(crc0, k0);
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t1 = (uint64_t)vmull_p64(crc1, k1);
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/* Merge (crc0, crc1, crc2) -> crc */
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crc1 = crc32c_u64(0, t1);
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crc ^= crc1;
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crc0 = crc32c_u64(0, t0);
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crc ^= crc0;
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length -= 1024;
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}
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if (length == 0) return crc ^ (0xffffffffU);
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#endif
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buf8 = (const uint8_t *)buf64;
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while (length >= 8) {
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crc = crc32c_u64(crc, *(const uint64_t *)buf8);
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buf8 += 8;
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length -= 8;
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}
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/* The following is more efficient than the straight loop */
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if (length >= 4) {
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crc = crc32c_u32(crc, *(const uint32_t *)buf8);
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buf8 += 4;
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length -= 4;
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}
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if (length >= 2) {
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crc = crc32c_u16(crc, *(const uint16_t *)buf8);
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buf8 += 2;
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length -= 2;
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}
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if (length >= 1) crc = crc32c_u8(crc, *buf8);
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crc ^= 0xffffffff;
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return crc;
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}
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#endif
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